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XCV100E-6BG352C

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XCV100E-6BG352C

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Part Number XCV100E-6BG352C
Manufacturer Xilinx Inc.
Description IC FPGA 196 I/O 352MBGA
Datasheet XCV100E-6BG352C Datasheet
Package 352-LBGA, Metal
In Stock 241 piece(s)
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Part Number # XCV100E-6BG352C (Embedded - FPGAs (Field Programmable Gate Array)) is manufactured by Xilinx Inc. and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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XCV100E-6BG352C Specifications

ManufacturerXilinx Inc.
CategoryIntegrated Circuits (ICs) - Embedded - FPGAs (Field Programmable Gate Array)
Datasheet XCV100E-6BG352CDatasheet
Package352-LBGA, Metal
SeriesVirtex?-E
Number of LABs/CLBs600
Number of Logic Elements/Cells2700
Total RAM Bits81920
Number of I/O196
Number of Gates128236
Voltage - Supply1.71 V ~ 1.89 V
Mounting TypeSurface Mount
Operating Temperature0°C ~ 85°C (TJ)
Package / Case352-LBGA, Metal
Supplier Device Package352-MBGA (35x35)

XCV100E-6BG352C Datasheet

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— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — Features • Fast, High-Density 1.8 V FPGA Family - Densities from 58 k to 4 M system gates - 130 MHz internal performance (four LUT levels) - Designed for low-power operation - PCI compliant 3.3 V, 32/64-bit, 33/ 66-MHz • Highly Flexible SelectI/O+™ Technology - Supports 20 high-performance interface standards - Up to 804 singled-ended I/Os or 344 differential I/O pairs for an aggregate bandwidth of > 100 Gb/s • Differential Signalling Support - LVDS (622 Mb/s), BLVDS (Bus LVDS), LVPECL - Differential I/O signals can be input, output, or I/O - Compatible with standard differential devices - LVPECL and LVDS clock inputs for 300+ MHz clocks • Proprietary High-Performance SelectLink™ Technology - Double Data Rate (DDR) to Virtex-E link - Web-based HDL generation methodology • Sophisticated SelectRAM+™ Memory Hierarchy - 1 Mb of internal configurable distributed RAM - Up to 832 Kb of synchronous internal block RAM - True Dual-Port BlockRAM capability - Memory bandwidth up to 1.66 Tb/s (equivalent bandwidth of over 100 RAMBUS channels) - Designed for high-performance Interfaces to External Memories - 200 MHz ZBT* SRAMs - 200 Mb/s DDR SDRAMs - Supported by free Synthesizable reference design • High-Performance Built-In Clock Management Circuitry - Eight fully digital Delay-Locked Loops (DLLs) - Digitally-Synthesized 50% duty cycle for Double Data Rate (DDR) Applications - Clock Multiply and Divide - Zero-delay conversion of high-speed LVPECL/LVDS clocks to any I/O standard • Flexible Architecture Balances Speed and Density - Dedicated carry logic for high-speed arithmetic - Dedicated multiplier support - Cascade chain for wide-input function - Abundant registers/latches with clock enable, and dual synchronous/asynchronous set and reset - Internal 3-state bussing - IEEE 1149.1 boundary-scan logic - Die-temperature sensor diode • Supported by Xilinx Foundation™ and Alliance Series™ Development Systems - Further compile time reduction of 50% - Internet Team Design (ITD) tool ideal for million-plus gate density designs - Wide selection of PC and workstation platforms • SRAM-Based In-System Configuration - Unlimited re-programmability • Advanced Packaging Options - 0.8 mm Chip-scale - 1.0 mm BGA - 1.27 mm BGA - HQ/PQ • 0.18 μm 6-Layer Metal Process • 100% Factory Tested * ZBT is a trademark of Integrated Device Technology, Inc. 0 Virtex™-E 1.8 V Field Programmable Gate Arrays DS022-1 (v3.0) March 21, 2014 0 0 Production Product Specification R © 2000-2014 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS022-1 (v3.0) March 21, 2014 www.xilinx.com Module 1 of 4 Production Product Specification 1

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Virtex™-E 1.8 V Field Programmable Gate Arrays R — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —Virtex-E Compared to Virtex Devices The Virtex-E family offers up to 43,200 logic cells in devices up to 30% faster than the Virtex family. I/O performance is increased to 622 Mb/s using Source Synchronous data transmission architectures and synchro- nous system performance up to 240 MHz using sin- gled-ended SelectI/O technology. Additional I/O standards are supported, notably LVPECL, LVDS, and BLVDS, which use two pins per signal. Almost all signal pins can be used for these new standards. Virtex-E devices have up to 640 Kb of faster (250 MHz) block SelectRAM, but the individual RAMs are the same size and structure as in the Virtex family. They also have eight DLLs instead of the four in Virtex devices. Each indi- vidual DLL is slightly improved with easier clock mirroring and 4x frequency multiplication. VCCINT, the supply voltage for the internal logic and mem- ory, is 1.8 V, instead of 2.5 V for Virtex devices. Advanced processing and 0.18 μm design rules have resulted in smaller dice, faster speed, and lower power consumption. I/O pins are 3 V tolerant, and can be 5 V tolerant with an external 100 Ω resistor. PCI 5 V is not supported. With the addition of appropriate external resistors, any pin can toler- ate any voltage desired. Banking rules are different. With Virtex devices, all input buffers are powered by VCCINT. With Virtex-E devices, the LVTTL, LVCMOS2, and PCI input buffers are powered by the I/O supply voltage VCCO. The Virtex-E family is not bitstream-compatible with the Vir- tex family, but Virtex designs can be compiled into equiva- lent Virtex-E devices. The same device in the same package for the Virtex-E and Virtex families are pin-compatible with some minor excep- tions. See the data sheet pinout section for details. General Description The Virtex-E FPGA family delivers high-performance, high-capacity programmable logic solutions. Dramatic increases in silicon efficiency result from optimizing the new architecture for place-and-route efficiency and exploiting an aggressive 6-layer metal 0.18 μm CMOS process. These advances make Virtex-E FPGAs powerful and flexible alter- natives to mask-programmed gate arrays. The Virtex-E fam- ily includes the nine members in Table 1. Building on experience gained from Virtex FPGAs, the Virtex-E family is an evolutionary step forward in program- mable logic design. Combining a wide variety of program- mable system features, a rich hierarchy of fast, flexible interconnect resources, and advanced process technology, the Virtex-E family delivers a high-speed and high-capacity programmable logic solution that enhances design flexibility while reducing time-to-market. Virtex-E Architecture Virtex-E devices feature a flexible, regular architecture that comprises an array of configurable logic blocks (CLBs) sur- rounded by programmable input/output blocks (IOBs), all interconnected by a rich hierarchy of fast, versatile routing Table 1: Virtex-E Field-Programmable Gate Array Family Members Device System Gates Logic Gates CLB Array Logic Cells Differential I/O Pairs User I/O BlockRAM Bits Distributed RAM Bits XCV50E 71,693 20,736 16 x 24 1,728 83 176 65,536 24,576 XCV100E 128,236 32,400 20 x 30 2,700 83 196 81,920 38,400 XCV200E 306,393 63,504 28 x 42 5,292 119 284 114,688 75,264 XCV300E 411,955 82,944 32 x 48 6,912 137 316 131,072 98,304 XCV400E 569,952 129,600 40 x 60 10,800 183 404 163,840 153,600 XCV600E 985,882 186,624 48 x 72 15,552 247 512 294,912 221,184 XCV1000E 1,569,178 331,776 64 x 96 27,648 281 660 393,216 393,216 XCV1600E 2,188,742 419,904 72 x 108 34,992 344 724 589,824 497,664 XCV2000E 2,541,952 518,400 80 x 120 43,200 344 804 655,360 614,400 XCV2600E 3,263,755 685,584 92 x 138 57,132 344 804 753,664 812,544 XCV3200E 4,074,387 876,096 104 x 156 73,008 344 804 851,968 1,038,336Module 1 of 4 www.xilinx.com DS022-1 (v3.0) March 21, 2014 2 Production Product Specification

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Virtex™-E 1.8 V Field Programmable Gate Arrays R — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —resources. The abundance of routing resources permits the Virtex-E family to accommodate even the largest and most complex designs. Virtex-E FPGAs are SRAM-based, and are customized by loading configuration data into internal memory cells. Con- figuration data can be read from an external SPROM (mas- ter serial mode), or can be written into the FPGA (SelectMAP™, slave serial, and JTAG modes). The standard Xilinx Foundation Series™ and Alliance Series™ Development systems deliver complete design support for Virtex-E, covering every aspect from behavioral and schematic entry, through simulation, automatic design translation and implementation, to the creation and down- loading of a configuration bit stream. Higher Performance Virtex-E devices provide better performance than previous generations of FPGAs. Designs can achieve synchronous system clock rates up to 240 MHz including I/O or 622 Mb/s using Source Synchronous data transmission architech- tures. Virtex-E I/Os comply fully with 3.3 V PCI specifica- tions, and interfaces can be implemented that operate at 33 MHz or 66 MHz. While performance is design-dependent, many designs operate internally at speeds in excess of 133 MHz and can achieve over 311 MHz. Table 2 shows performance data for representative circuits, using worst-case timing parameters. Virtex-E Device/Package Combinations and Maximum I/O Table 2: Performance for Common Circuit Functions Function Bits Virtex-E (-7) Register-to-Register Adder 16 64 4.3 ns 6.3 ns Pipelined Multiplier 8 x 8 16 x 16 4.4 ns 5.1 ns Address Decoder 16 64 3.8 ns 5.5 ns 16:1 Multiplexer 4.6 ns Parity Tree 9 18 36 3.5 ns 4.3 ns 5.9 ns Chip-to-Chip HSTL Class IV LVTTL,16mA, fast slew LVDS LVPECL Table 3: Virtex-E Family Maximum User I/O by Device/Package (Excluding Dedicated Clock Pins) XCV 50E XCV 100E XCV 200E XCV 300E XCV 400E XCV 600E XCV 1000E XCV 1600E XCV 2000E XCV 2600E XCV 3200E CS144 94 94 94 PQ240 158 158 158 158 158 HQ240 158 158 BG352 196 260 260 BG432 316 316 316 BG560 404 404 404 404 404 FG256 176 176 176 176 FG456 284 312 FG676 404 444 FG680 512 512 512 512 FG860 660 660 660 FG900 512 660 700 FG1156 660 724 804 804 804DS022-1 (v3.0) March 21, 2014 www.xilinx.com Module 1 of 4 Production Product Specification 3

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Virtex™-E 1.8 V Field Programmable Gate Arrays R — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —Virtex-E Ordering Information Revision History The following table shows the revision history for this document. Figure 1: Ordering Information Date Version Revision 12/07/1999 1.0 Initial Xilinx release. 01/10/2000 1.1 Re-released with spd.txt v. 1.18, FG860/900/1156 package information, and additional DLL, Select RAM and SelectI/O information. 01/28/2000 1.2 Added Delay Measurement Methodology table, updated SelectI/O section, Figures 30, 54, & 55, text explaining Table 5, TBYP values, buffered Hex Line info, p. 8, I/O Timing Measurement notes, notes for Tables 15, 16, and corrected F1156 pinout table footnote references. 02/29/2000 1.3 Updated pinout tables, VCC page 20, and corrected Figure 20. 05/23/2000 1.4 Correction to table on p. 22. 07/10/2000 1.5 • Numerous minor edits. • Data sheet upgraded to Preliminary. • Preview -8 numbers added to Virtex-E Electrical Characteristics tables. 08/01/2000 1.6 • Reformatted entire document to follow new style guidelines. • Changed speed grade values in tables on pages 35-37. 09/20/2000 1.7 • Min values added to Virtex-E Electrical Characteristics tables. • XCV2600E and XCV3200E numbers added to Virtex-E Electrical Characteristics tables (Module 3). • Corrected user I/O count for XCV100E device in Table 1 (Module 1). • Changed several pins to “No Connect in the XCV100E“ and removed duplicate VCCINT pins in Table ~ (Module 4). • Changed pin J10 to “No connect in XCV600E” in Table 74 (Module 4). • Changed pin J30 to “VREF option only in the XCV600E” in Table 74 (Module 4). • Corrected pair 18 in Table 75 (Module 4) to be “AO in the XCV1000E, XCV1600E“. Example: XCV300E-6PQ240C Device Type Temperature Range C = Commercial (Tj = 0 C to +85 C) I = Industrial (Tj = -40 C to +100 C) Number of Pins Package Type BG = Ball Grid Array FG = Fine Pitch Ball Grid Array HQ = High Heat Dissipation Speed Grade (-6, -7, -8) DS022_043_072000Module 1 of 4 www.xilinx.com DS022-1 (v3.0) March 21, 2014 4 Production Product Specification

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Virtex™-E 1.8 V Field Programmable Gate Arrays R — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —Virtex-E Data Sheet The Virtex-E Data Sheet contains the following modules: • DS022-1, Virtex-E 1.8V FPGAs: Introduction and Ordering Information (Module 1) • DS022-2, Virtex-E 1.8V FPGAs: Functional Description (Module 2) • DS022-3, Virtex-E 1.8V FPGAs: DC and Switching Characteristics (Module 3) • DS022-4, Virtex-E 1.8V FPGAs: Pinout Tables (Module 4) 11/20/2000 1.8 • Upgraded speed grade -8 numbers in Virtex-E Electrical Characteristics tables to Preliminary. • Updated minimums in Table 13 and added notes to Table 14. • Added to note 2 to Absolute Maximum Ratings. • Changed speed grade -8 numbers for TSHCKO32, TREG, TBCCS, and TICKOF. • Changed all minimum hold times to –0.4 under Global Clock Setup and Hold for LVTTL Standard, with DLL. • Revised maximum TDLLPW in -6 speed grade for DLL Timing Parameters. • Changed GCLK0 to BA22 for FG860 package in Table 46. 02/12/2001 1.9 • Revised footnote for Table 14. • Added numbers to Virtex-E Electrical Characteristics tables for XCV1000E and XCV2000E devices. • Updated Table 27 and Table 78 to include values for XCV400E and XCV600E devices. • Revised Table 62 to include pinout information for the XCV400E and XCV600E devices in the BG560 package. • Updated footnotes 1 and 2 for Table 76 to include XCV2600E and XCV3200E devices. 04/02/2001 2.0 • Updated numerous values in Virtex-E Switching Characteristics tables. • Converted data sheet to modularized format. See the Virtex-E Data Sheet section. 10/25/2001 2.1 • Updated the Virtex-E Device/Package Combinations and Maximum I/O table to show XCV3200E in the FG1156 package. 11/09/2001 2.2 • Minor edits. 07/17/2002 2.3 • Data sheet designation upgraded from Preliminary to Production. 03/21/2014 3.0 • This product is obsolete/discontinued per XCN09001 and XCN12026. Date Version RevisionDS022-1 (v3.0) March 21, 2014 www.xilinx.com Module 1 of 4 Production Product Specification 5

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Virtex™-E 1.8 V Field Programmable Gate Arrays R — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —Module 1 of 4 www.xilinx.com DS022-1 (v3.0) March 21, 2014 6 Production Product Specification

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— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE — Architectural Description Virtex-E Array The Virtex-E user-programmable gate array, shown in Figure 1, comprises two major configurable elements: con- figurable logic blocks (CLBs) and input/output blocks (IOBs). • CLBs provide the functional elements for constructing logic • IOBs provide the interface between the package pins and the CLBs CLBs interconnect through a general routing matrix (GRM). The GRM comprises an array of routing switches located at the intersections of horizontal and vertical routing channels. Each CLB nests into a VersaBlock™ that also provides local routing resources to connect the CLB to the GRM. The VersaRing™ I/O interface provides additional routing resources around the periphery of the device. This routing improves I/O routability and facilitates pin locking. The Virtex-E architecture also includes the following circuits that connect to the GRM. • Dedicated block memories of 4096 bits each • Clock DLLs for clock-distribution delay compensation and clock domain control • 3-State buffers (BUFTs) associated with each CLB that drive dedicated segmentable horizontal routing resources Values stored in static memory cells control the configurable logic elements and interconnect resources. These values load into the memory cells on power-up, and can reload if necessary to change the function of the device. Input/Output Block The Virtex-E IOB, Figure 2, features SelectI/O+ inputs and outputs that support a wide variety of I/O signalling stan- dards, see Table 1. The three IOB storage elements function either as edge-triggered D-type flip-flops or as level-sensitive latches. Each IOB has a clock signal (CLK) shared by the three flip-flops and independent clock enable signals for each flip-flop. 0 Virtex™-E 1.8 V Field Programmable Gate Arrays DS022-2 (v3.0) March 21, 2014 0 0 Production Product Specification R Figure 1: Virtex-E Architecture Overview DLLDLL IO B s IO B s VersaRing VersaRing ds022_01_121099 C L B s B R A M s B R A M s B R A M s C L B s C L B s B R A M s C L B s DLLDLL DLLDLLDLLDLL Figure 2: Virtex-E Input/Output Block (IOB) OBUFT IBUF Vref ds022_02_091300 SR CLK ICE OCE O I IQ T TCE D CE Q SR D CE Q SR D CE Q SR PAD Programmable Delay Weak Keeper© 2000-2014 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS022-2 (v3.0) March 21, 2014 www.xilinx.com Module 2 of 4 Production Product Specification 1

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Virtex™-E 1.8 V Field Programmable Gate Arrays R — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —In addition to the CLK and CE control signals, the three flip-flops share a Set/Reset (SR). For each flip-flop, this sig- nal can be independently configured as a synchronous Set, a synchronous Reset, an asynchronous Preset, or an asyn- chronous Clear. The output buffer and all of the IOB control signals have independent polarity controls. All pads are protected against damage from electrostatic discharge (ESD) and from over-voltage transients. After configuration, clamping diodes are connected to VCCO with the exception of LVCMOS18, LVCMOS25, GTL, GTL+, LVDS, and LVPECL. Optional pull-up, pull-down and weak-keeper circuits are attached to each pad. Prior to configuration all outputs not involved in configuration are forced into their high-imped- ance state. The pull-down resistors and the weak-keeper circuits are inactive, but I/Os can optionally be pulled up. The activation of pull-up resistors prior to configuration is controlled on a global basis by the configuration mode pins. If the pull-up resistors are not activated, all the pins are in a high-impedance state. Consequently, external pull-up or pull-down resistors must be provided on pins required to be at a well-defined logic level prior to configuration. All Virtex-E IOBs support IEEE 1149.1-compatible Bound- ary Scan testing. Input Path The Virtex-E IOB input path routes the input signal directly to internal logic and/ or through an optional input flip-flop. An optional delay element at the D-input of this flip-flop elim- inates pad-to-pad hold time. The delay is matched to the internal clock-distribution delay of the FPGA, and when used, assures that the pad-to-pad hold time is zero. Each input buffer can be configured to conform to any of the low-voltage signalling standards supported. In some of these standards the input buffer utilizes a user-supplied threshold voltage, VREF. The need to supply VREF imposes constraints on which standards can be used in close prox- imity to each other. See I/O Banking. There are optional pull-up and pull-down resistors at each user I/O input for use after configuration. Their value is in the range 50 – 100 kΩ. Output Path The output path includes a 3-state output buffer that drives the output signal onto the pad. The output signal can be routed to the buffer directly from the internal logic or through an optional IOB output flip-flop. The 3-state control of the output can also be routed directly from the internal logic or through a flip-flip that provides syn- chronous enable and disable. Each output driver can be individually programmed for a wide range of low-voltage signalling standards. Each output buffer can source up to 24 mA and sink up to 48 mA. Drive strength and slew rate controls minimize bus transients. In most signalling standards, the output High voltage depends on an externally supplied VCCO voltage. The need to supply VCCO imposes constraints on which standards can be used in close proximity to each other. See I/O Bank- ing. An optional weak-keeper circuit is connected to each out- put. When selected, the circuit monitors the voltage on the pad and weakly drives the pin High or Low to match the input signal. If the pin is connected to a multiple-source sig- nal, the weak keeper holds the signal in its last state if all drivers are disabled. Maintaining a valid logic level in this way eliminates bus chatter. Since the weak-keeper circuit uses the IOB input buffer to monitor the input level, an appropriate VREF voltage must be provided if the signalling standard requires one. The provi- sion of this voltage must comply with the I/O banking rules. I/O Banking Some of the I/O standards described above require VCCO and/or VREF voltages. These voltages are externally sup- plied and connected to device pins that serve groups of IOBs, called banks. Consequently, restrictions exist about which I/O standards can be combined within a given bank. Table 1: Supported I/O Standards I/O Standard Output VCCO Input VCCO Input VREF Board Termination Voltage (VTT) LVTTL 3.3 3.3 N/A N/A LVCMOS2 2.5 2.5 N/A N/A LVCMOS18 1.8 1.8 N/A N/A SSTL3 I & II 3.3 N/A 1.50 1.50 SSTL2 I & II 2.5 N/A 1.25 1.25 GTL N/A N/A 0.80 1.20 GTL+ N/A N/A 1.0 1.50 HSTL I 1.5 N/A 0.75 0.75 HSTL III & IV 1.5 N/A 0.90 1.50 CTT 3.3 N/A 1.50 1.50 AGP-2X 3.3 N/A 1.32 N/A PCI33_3 3.3 3.3 N/A N/A PCI66_3 3.3 3.3 N/A N/A BLVDS & LVDS 2.5 N/A N/A N/A LVPECL 3.3 N/A N/A N/AModule 2 of 4 www.xilinx.com DS022-2 (v3.0) March 21, 2014 2 Production Product Specification

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Virtex™-E 1.8 V Field Programmable Gate Arrays R — OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —Eight I/O banks result from separating each edge of the FPGA into two banks, as shown in Figure 3. Each bank has multiple VCCO pins, all of which must be connected to the same voltage. This voltage is determined by the output standards in use. Within a bank, output standards can be mixed only if they use the same VCCO. Compatible standards are shown in Table 2. GTL and GTL+ appear under all voltages because their open-drain outputs do not depend on VCCO. Some input standards require a user-supplied threshold voltage, VREF. In this case, certain user-I/O pins are auto- matically configured as inputs for the VREF voltage. Approx- imately one in six of the I/O pins in the bank assume this role. The VREF pins within a bank are interconnected internally and consequently only one VREF voltage can be used within each bank. All VREF pins in the bank, however, must be con- nected to the external voltage source for correct operation. Within a bank, inputs that require VREF can be mixed with those that do not. However, only one VREF voltage can be used within a bank. In Virtex-E, input buffers with LVTTL, LVCMOS2, LVCMOS18, PCI33_3, PCI66_3 standards are supplied by VCCO rather than VCCINT. For these standards, only input and output buffers that have the same VCCO can be mixed together. The VCCO and VREF pins for each bank appear in the device pin-out tables and diagrams. The diagrams also show the bank affiliation of each I/O. Within a given package, the number of VREF and VCCO pins can vary depending on the size of device. In larger devices, more I/O pins convert to VREF pins. Since these are always a super set of the VREF pins used for smaller devices, it is possible to design a PCB that permits migration to a larger device if necessary. All the VREF pins for the largest device anticipated must be connected to the VREF voltage, and not used for I/O. In smaller devices, some VCCO pins used in larger devices do not connect within the package. These unconnected pins can be left unconnected externally, or can be connected to the VCCO voltage to permit migration to a larger device if necessary. Configurable Logic Blocks The basic building block of the Virtex-E CLB is the logic cell (LC). An LC includes a 4-input function generator, carry logic, and a storage element. The output from the function generator in each LC drives both the CLB output and the D input of the flip-flop. Each Virtex-E CLB contains four LCs, organized in two similar slices, as shown in Figure 4. Figure 5 shows a more detailed view of a single slice. In addition to the four basic LCs, the Virtex-E CLB contains logic that combines function generators to provide functions of five or six inputs. Consequently, when estimating the number of system gates provided by a given device, each CLB counts as 4.5 LCs. Look-Up Tables Virtex-E function generators are implemented as 4-input look-up tables (LUTs). In addition to operating as a function generator, each LUT can provide a 16 x 1-bit synchronous RAM. Furthermore, the two LUTs within a slice can be com- bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM, or a 16 x 1-bit dual-port synchronous RAM. The Virtex-E LUT can also provide a 16-bit shift register that is ideal for capturing high-speed or burst-mode data. This mode can also be used to store data in applications such as Digital Signal Processing. Figure 3: Virtex-E I/O Banks Table 2: Compatible Output Standards VCCO Compatible Standards 3.3 V PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL, GTL+, LVPECL 2.5 V SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+, BLVDS, LVDS 1.8 V LVCMOS18, GTL, GTL+ 1.5 V HSTL I, HSTL III, HSTL IV, GTL, GTL+ ds022_03_121799 Bank 0 GCLK3 GCLK2 GCLK1 GCLK0 Bank 1 Bank 5 Bank 4 VirtexE Device B a n k 7 B a n k 6 B a n k 2 B a n k 3DS022-2 (v3.0) March 21, 2014 www.xilinx.com Module 2 of 4 Production Product Specification 3

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RNF14BTD7K87 RNF14BTD7K87 Stackpole Electronics Inc., RES 7.87K OHM 1/4W .1% AXIAL, Axial, Virtex?-E View
HM11-11503LF HM11-11503LF TT Electronics/BI Magnetics, FIXED IND 11UH 12A 8.1 MOHM TH, Radial, Virtex?-E View
181902-1 181902-1 TE Connectivity AMP Connectors, CONN QC RCPT 18-22AWG 0.250, -, Virtex?-E View
1771860000 1771860000 Weidmuller, SPP ZTL 6, -, Virtex?-E View
FTMH-128-03-L-DH FTMH-128-03-L-DH Samtec Inc., CONN HEADER 56POS DL 1MM R/A SMD, -, Virtex?-E View
JMXHH1G08FSUDSG JMXHH1G08FSUDSG Souriau, CONN RCPT FMALE 8POS GOLD SOLDER, -, Virtex?-E View
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XCV100E-6BG352C

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