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IRF9610STRL

hot IRF9610STRL

IRF9610STRL

For Reference Only

Part Number IRF9610STRL
Manufacturer Vishay Siliconix
Description MOSFET P-CH 200V 1.8A D2PAK
Datasheet IRF9610STRL Datasheet
Package TO-263-3, D2Pak (2 Leads + Tab), TO-263AB
In Stock 6400 piece(s)
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IRF9610STRL Specifications

ManufacturerVishay Siliconix
CategoryDiscrete Semiconductor Products - Transistors - FETs, MOSFETs - Single
Datasheet IRF9610STRL Datasheet
PackageTO-263-3, D2Pak (2 Leads + Tab), TO-263AB
Series-
FET TypeP-Channel
TechnologyMOSFET (Metal Oxide)
Drain to Source Voltage (Vdss)200V
Current - Continuous Drain (Id) @ 25��C1.8A (Tc)
Drive Voltage (Max Rds On, Min Rds On)10V
Vgs(th) (Max) @ Id4V @ 250µA
Gate Charge (Qg) (Max) @ Vgs11nC @ 10V
Input Capacitance (Ciss) (Max) @ Vds170pF @ 25V
Vgs (Max)��20V
Power Dissipation (Max)3W (Ta), 20W (Tc)
Rds On (Max) @ Id, Vgs3 Ohm @ 900mA, 10V
Operating Temperature-55°C ~ 150°C (TJ)
Mounting TypeSurface Mount
Supplier Device PackageD2PAK
Package / CaseTO-263-3, D2Pak (2 Leads + Tab), TO-263AB

IRF9610STRL Datasheet

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IRF9610S, SiHF9610S www.vishay.com Vishay Siliconix S12-1558-Rev. D, 02-Jul-12 1 Document Number: 91081 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Power MOSFET FEATURES • Surface Mount • Available in Tape and Reel • Dynamic dV/dt Rating • P-Channel • Fast Switching • Ease of Paralleling • Simple Drive Requirements • Material categorization: For definitions of compliance please see www.vishay.com/doc?99912 Note * Lead (Pb)-containing terminations are not RoHS-compliant. Exemptions may apply. DESCRIPTION Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The D2PAK (TO-263) is a surface mount power package capable of accommodating die sizes up to HEX-4. It provides the highest power capability and the lowest possible on-resistance in any existing surface mount package. The D2PAK (TO-263) is suitable for high current applications because of its low internal connection resistance and can dissipate up to 2 W in a typical surface mount application. Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 5). b. ISD  - 1.8 A, dI/dt  70 A/μs, VDD  VDS, TJ  150 °C. c. 1.6 mm from case. d. When mounted on 1" square PCB (FR-4 or G-10 material). PRODUCT SUMMARY VDS (V) - 200 RDS(on) () VGS = - 10 V 3 Qg (Max.) (nC) 11 Qgs (nC) 7 Qgd (nC) 4 Configuration Single S G D P-Channel MOSFET D2PAK (TO-263) G D S ORDERING INFORMATION Package D2PAK (TO-263) Lead (Pb)-free and Halogen-free SiHF9610S-GE3 SiHF9610STRR-GE3 SiHF9610STRL-GE3 Lead (Pb)-free IRF9610SPbF SiHF9610S-E3 IRF9610STRRPbF IRF9610STRLPbF ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT UNIT Drain-Source Voltage VDS - 200 V Gate-Source Voltage VGS ± 20 Continuous Drain Current VGS at - 10 V TC = 25 °C ID - 1.8 ATC = 100 °C - 1 Pulsed Drain Currenta IDM - 7 Linear Derating Factor 0.16 W/°C Linear Derating Factor (PCB Mount)d 0.025 Maximum Power Dissipation TC = 25 °C PD 20 W Maximum Power Dissipation (PCB Mount)d TA = 25 °C 3 Peak Diode Recovery dV/dtb dV/dt - 5 V/ns Operating Junction and Storage Temperature Range TJ, Tstg - 55 to + 150 °C Soldering Recommendations (Peak Temperature) for 10 s 300c

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IRF9610S, SiHF9610S www.vishay.com Vishay Siliconix S12-1558-Rev. D, 02-Jul-12 2 Document Number: 91081 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Note a. When mounted on 1" square PCB (FR-4 or G-10 material). Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 5). b. Pulse width  300 μs; duty cycle  2 %. THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. UNIT Maximum Junction-to-Ambient RthJA - 62 °C/W Maximum Junction-to-Ambient (PCB Mount)a RthJA - 40 Maximum Junction-to-Case (Drain) RthJC - 6.4 SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS VGS = 0, ID = - 250 μA - 200 - - V VDS Temperature Coefficient VDS/TJ Reference to 25 °C, ID = - 1 mA - - 0.23 - V/°C Gate-Source Threshold Voltage VGS(th) VDS = VGS, ID = - 250 μA - 2 - - 4 V Gate-Source Leakage IGSS VGS = ± 20 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = - 200 V, VGS = 0 V - - - 100 μA VDS = - 160 V, VGS = 0 V, TJ = 125 °C - - - 500 Drain-Source On-State Resistance RDS(on) VGS = - 10 V ID = - 0.90 A b - - 3  Forward Transconductance gfs VDS = - 50 V, ID = - 0.90 A b 0.90 - - S Dynamic Input Capacitance Ciss VGS = 0 V, VDS = - 25 V, f = 1 MHz, see fig. 10 - 170 - pFOutput Capacitance Coss - 50 - Reverse Transfer Capacitance Crss - 15 - Total Gate Charge Qg VGS = - 10 V ID = - 3.5 A, VDS = - 160 V, see fig. 11 and 18b - - 11 nC Gate-Source Charge Qgs - - 7 Gate-Drain Charge Qgd - - 4 Turn-On Delay Time td(on) VDD = - 100 V, ID = - 0.90 A, RG = 50 , RD = 110 , see fig. 17b - 8 - ns Rise Time tr - 15 - Turn-Off Delay Time td(off) - 1 - Fall Time tf - 8 - Internal Drain Inductance LD Between lead, 6 mm (0.25") from package and center of die contact - 4.5 - nH Internal Source Inductance LS - 7.5 - Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS MOSFET symbol showing the integral reverse p - n junction diode - - - 1.8 A Pulsed Diode Forward Currenta ISM - - - 7 Body Diode Voltage VSD TJ = 25 °C, IS = - 1.8 A, VGS = 0 V b - - - 5.8 V Body Diode Reverse Recovery Time trr TJ = 25 °C, IF = - 1.8 A, dI/dt = 100 A/μs b - 240 360 ns Body Diode Reverse Recovery Charge Qrr - 1.7 2.6 μC Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) D S G S D G

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IRF9610S, SiHF9610S www.vishay.com Vishay Siliconix S12-1558-Rev. D, 02-Jul-12 3 Document Number: 91081 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) Fig. 1 - Typical Output Characteristics Fig. 2 - Typical Transfer Characteristics Fig. 3 - Typical Saturation Characteristics Fig. 4 - Maximum Safe Operating Area Fig. 5 - Maximum Effective Transient Thermal Impedance, Junction-to.Case vs. Pulse Duration 91081_01 VDS, Drain-to-Source Voltage (V) I D , D ra in C u rr e n t (A ) - 10 - 2.40 - 4 V - 6 V - 5 V VGS = - 10, - 9, - 8, - 7 V - 1.92 - 1.44 - 0.96 - 0.48 0.00 0 - 20 - 30 - 40 - 50 80 µs Pulse Test VGS, Gate-to-Source Voltage (V) I D , D ra in C u rr e n t (A ) 80 µs Pulse Test VDS > ID(on) x RDS(on) max. 91081_02 - 2 - 2.40 - 1.92 - 1.44 - 0.96 - 0.48 0.00 0 - 4 - 6 - 8 - 10 TJ = - 55 °C TJ = 25 °C TJ = 125 °C 80 µs Pulse Test I D , D ra in C u rr e n t (A ) VDS, Drain-to-Source Voltage (V)91081_03 - 4 V - 6 V - 5 V VGS = - 10, - 9, - 8 V - 7 V - 2 - 2.40 - 1.92 - 1.44 - 0.96 - 0.48 0.00 0 - 4 - 6 - 8 - 10 100 µs 1 ms 10 ms Operation in this area limited by RDS(on) Negative VDS, Drain-to-Source Voltage (V) N e g a ti v e I D , D ra in C u rr e n t (A ) TC = 25 °C TJ = 150 °C Single Pulse 102 2 5 0.1 1 2 5 10 2 5 2 5 1 10 2 5 102 103 2 5 91081_04 2.0 1.0 0.1 10-5 10-4 10-3 10-2 0.1 1.0 10 PDM t1 t2 t1, Square Wave Pulse Duration (s) Z th J C (t )/ R th J C , N o rm a liz e d E ff e c ti v e T ra n s ie Notes: 1. Duty Factor, D = t1/t2 2. Per Unit Base = RthJC = 6.4 °C/W 3. TJM - TC = PDM ZthJC(t) 0.2 0.05 0.02 0.01 91081_05 0.1 D = 0.50.5 0.2 0.05 0.02 0.01 2 5 2 5 2 5 2 5 2 5 2 5 T h e rm a l Im p e d e n c e ( P e r U n it ) Single Pulse (Transient Thermal Impedence)

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IRF9610S, SiHF9610S www.vishay.com Vishay Siliconix S12-1558-Rev. D, 02-Jul-12 4 Document Number: 91081 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Fig. 6 - Typical Transconductance vs. Drain Current Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Breakdown Voltage vs. Temperature Fig. 9 - Normalized On-Resistance vs. Temperature Fig. 10 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 11 - Typical Gate Charge vs. Gate-to-Source Voltage 2.0 g fs ,T ra n s c o n d u c ta n c e ( S ) ID, Drain Current (A) - 0.48 - 0.96 - 1.44 - 1.92 - 2.400 TJ = 25 °C TJ = - 55 °C 91081_06 TJ = 125 °C 80 µs Pulse Test VDS > ID(on) x RDS(on) max. 1.6 1.2 0.8 0.4 0.0 TJ = 25 °C TJ = 150 °C - 10.0 VSD, Source-to-Drain Voltage (V) I D , D ra in C u rr e n t (A ) - 2.0 - 6.8- 5.6- 4.4- 3.2 91081_07 - 0.1 - 0.2 - 0.5 - 1.0 - 2.0 - 5.0 - 8.0 91081_08 TJ, Junction Temperature (°C) B V D S S , D ra in -t o -S o u rc e B re a k d o w n 1.25 V o lt a g e ( N o rm a liz e d ) 1.15 0.75 0.85 0.95 1.05 - 40 16012080400 91081_09 TJ, Junction Temperature (°C) R D S (o n ), D ra in -t o -S o u rc e O n R e s is ta n c e 2.5 (N o rm a liz e d ) 2.0 0.0 0.5 1.0 1.5 - 40 16012080400 ID = - 0.6 A VGS = - 10 V 91081_10 VDS, Drain-to-Source Voltage (V) C , C a p a c it a n c e ( p F ) 500 0 100 200 300 400 0 - 50- 40- 30- 20- 10 Ciss Crss Coss VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgs, Cgd Cgs + Cgd ≈ Cgs + Cgd QG, Total Gate Charge (nC) N e g a ti v e V G S , G a te -t o -S o u rc e V o lt a g e ( V ) 20 16 12 8 0 4 0 2 864 VDS = - 40 V VDS = - 60 V For test circuit see figure 18 VDS = - 100 V 91081_11 ID = - 1.8 A

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IRF9610S, SiHF9610S www.vishay.com Vishay Siliconix S12-1558-Rev. D, 02-Jul-12 5 Document Number: 91081 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Fig. 12 - Typical On-Resistance vs. Drain Current Fig. 13 - Maximum Drain Current vs. Case Temperature Fig. 14 - Power vs. Temperature Derating Curve Fig. 15 - Clamped Inductive Test Circuit Fig. 16 - Clamped Inductive Waveforms 91081_12 ID, Drain Current (A) R D S (o n ), D ra in -t o -S o u rc e 7 RDS(on) measured with current pulse of 2.0 µs duration. Initial TJ = 25 °C. (Heating effect of 2.0 µs pulse is minimal.) 6 0 1 2 3 4 5 0 - 7- 6- 1 - 2 - 3 - 4 - 5 O n R e s is ta n c e ( Ω ) VGS = - 10 V VGS = - 20 V 150 N e g a ti v e I D , D ra in C u rr e n t (A ) TC, Case Temperature (°C) 0.0 0.4 0.8 1.2 1.6 2.0 25 91081_13 1251007550 TC, Case Temperature (°C) P D , P o w e r D is s ip a ti o n ( W ) 20 15 10 0 5 0 20 100806040 91081_14 140120 0.05 Ω D.U.T. L VDS + -V DD VGS = - 10 V Vary tp to obtain required IL tp VDD = 0.5 VDS EC = 0.75 VDS EC IL VDD VDS tp EC IL

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IRF9610S, SiHF9610S www.vishay.com Vishay Siliconix S12-1558-Rev. D, 02-Jul-12 6 Document Number: 91081 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Fig. 17a - Switching Time Test Circuit Fig. 17b - Switching Time Waveforms Fig. 18a - Basic Gate Charge Waveform Fig. 18b - Gate Charge Test Circuit Pulse width ≤ 1 µs Duty factor ≤ 0.1 % RD VGS Rg D.U.T. - 10 V + - VDS VDD VGS 10 % 90 % VDS td(on) tr td(off) tf QGS QGD QG VG Charge - 10 V D.U.T. - 3 mA VGS VDS IG ID 0.3 µF 0.2 µF 50 kΩ 12 V Current regulator Current sampling resistors Same type as D.U.T. + -

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IRF9610S, SiHF9610S www.vishay.com Vishay Siliconix S12-1558-Rev. D, 02-Jul-12 7 Document Number: 91081 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Fig. 19 - For P-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91081. P.W. Period dI/dt Diode recovery dV/dt Body diode forward drop Body diode forward current Driver gate drive Inductor current D = P.W. Period + - - - - + + + Peak Diode Recovery dV/dt Test Circuit • dV/dt controlled by Rg • D.U.T. - device under test D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer Rg • Compliment N-Channel of D.U.T. for driver VDD• ISD controlled by duty factor “D” Note Note a. VGS = - 5 V for logic level and - 3 V drive devices VGS = - 10 V a D.U.T. lSD waveform D.U.T. VDS waveform VDD Re-applied voltage Ripple ≤ 5 % ISD Reverse recovery current

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Document Number: 91364 www.vishay.com Revision: 15-Sep-08 1 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. 5 4 1 3 L1 L2 D B B E H BA Detail A A A c c2 A 2 x e 2 x b2 2 x b 0.010 A BM M ± 0.004 BM Base metal Plating b1, b3 (b, b2) c1(c) Section B - B and C - C Scale: none Lead tip 4 3 4 (Datum A) 2 C C 5 5 View A - A E1 D1 E 4 4 B H Seating plane Gauge plane 0° to 8° Detail “A” Rotated 90° CW scale 8:1 L3 A1L4 L MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 b 0.51 0.99 0.020 0.039 E1 6.22 - 0.245 - b1 0.51 0.89 0.020 0.035 e 2.54 BSC 0.100 BSC b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 0.25 BSC 0.010 BSC D 8.38 9.65 0.330 0.380 L4 4.78 5.28 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970

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AN826 Vishay Siliconix Document Number: 73397 11-Apr-05 www.vishay.com 1 RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead 0. 63 5 (1 6. 12 9) Recommended Minimum Pads Dimensions in Inches/(mm) 0.420 (10.668) 0. 35 5 (9 .0 17 ) 0.145 (3.683) 0.135 (3.429) 0.200 (5.080) 0.050 (1.257) Return to Index

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Sam*****mesh

January 23, 2020

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October 6, 2019

Wish there were some documentation but I guess if you're buying you kinda should know.

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September 29, 2019

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September 15, 2019

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August 21, 2019

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August 19, 2019

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August 4, 2019

Super easy search and order process. Lots of Shipping and Payment Options, you can always find the best way for the purchase.

Mar***** Mani

August 1, 2019

Didn’t need so many but it was cheap. I did have to solder extra wire on each end to make fit better but exactly you need of your looking for this particular mod.

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