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STD70N2LH5

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STD70N2LH5

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Part Number STD70N2LH5
Manufacturer STMicroelectronics
Description MOSFET N-CH 25V 48A DPAK
Datasheet STD70N2LH5 Datasheet
Package TO-252-3, DPak (2 Leads + Tab), SC-63
In Stock 85,302 piece(s)
Unit Price Request a Quote
Lead Time Can Ship Immediately
Estimated Delivery Time Dec 7 - Dec 12 (Choose Expedited Shipping)
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Part Number # STD70N2LH5 (Transistors - FETs, MOSFETs - Single) is manufactured by STMicroelectronics and distributed by Heisener. Being one of the leading electronics distributors, we carry many kinds of electronic components from some of the world’s top class manufacturers. Their quality is guaranteed by its stringent quality control to meet all required standards.

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STD70N2LH5 Specifications

ManufacturerSTMicroelectronics
CategoryDiscrete Semiconductor Products - Transistors - FETs, MOSFETs - Single
Datasheet STD70N2LH5Datasheet
PackageTO-252-3, DPak (2 Leads + Tab), SC-63
SeriesSTripFET? V
FET TypeN-Channel
TechnologyMOSFET (Metal Oxide)
Drain to Source Voltage (Vdss)25V
Current - Continuous Drain (Id) @ 25°C48A (Tc)
Drive Voltage (Max Rds On, Min Rds On)5V, 10V
Vgs(th) (Max) @ Id1V @ 250µA
Gate Charge (Qg) (Max) @ Vgs8nC @ 5V
Input Capacitance (Ciss) (Max) @ Vds1300pF @ 25V
Vgs (Max)��22V
FET Feature-
Power Dissipation (Max)60W (Tc)
Rds On (Max) @ Id, Vgs7.1 mOhm @ 24A, 10V
Operating Temperature-55°C ~ 175°C (TJ)
Mounting TypeSurface Mount
Supplier Device PackageDPAK
Package / CaseTO-252-3, DPak (2 Leads + Tab), SC-63

STD70N2LH5 Datasheet

Page 1

Page 2

Preliminary Data This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. September 2008 Rev 2 1/12 12 STD70N2LH5 STU70N2LH5 N-channel 25 V, 0.006 Ω, 48 A - DPAK - IPAK STripFET™ V Power MOSFET Features ■ RDS(on) * Qg industry benchmark ■ Extremely low on-resistance RDS(on) ■ Very low switching gate charge ■ High avalanche ruggedness ■ Low gate drive power losses Application ■ Switching applications Description This product utilizes the 5th generation of design rules of ST’s proprietary STripFET™ technology. The lowest available RDS(on)*Qg, in the standard packages, makes this device suitable for the most demanding DC-DC converter applications, where high power density is to be achieved. Figure 1. Internal schematic diagram Type VDSS RDS(on) max ID STD70N2LH5 25 V 0.0071 Ω 48 A STU70N2LH5 25 V 0.0075 Ω 48 A DPAK 1 3 3 2 1 IPAK Table 1. Device summary Order codes Marking Package Packaging STD70N2LH5 70N2LH5 DPAK Tape & reel STU70N2LH5 70N2LH5 IPAK Tube www.st.com Ob so let e Pr od uc t(s ) - O bs ole te P ro du ct( s)

Page 3

Electrical ratings STD70N2LH5 - STU70N2LH5 2/12 1 Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage (VGS=0) 25 V VGS Gate-Source voltage ± 22 V ID (1) 1. Limited by wire bonding Drain current (continuous) at TC = 25 °C 48 A ID Drain current (continuous) at TC = 100 °C 43 A IDM (2) 2. Pulse width limited by safe operating area Drain current (pulsed) 192 A PTOT Total dissipation at TC = 25 °C 60 W Derating factor 0.4 W/°C EAS (3) 3. Starting Tj = 25 °C, ID = 24 A, VDD = 12 V Single pulse avalanche energy TBD mJ Tj Tstg Operating junction temperature Storage temperature -55 to 175 °C Table 3. Thermal resistance Symbol Parameter Value Unit Rthj-case Thermal resistance junction-case max 2.5 °C/W Rthj-amb Thermal resistance junction-case max 100 °C/W Tj Maximum lead temperature for soldering purpose 275 °C Ob so let e Pr od uc t(s ) - O bs ole te P ro du ct( s)

Page 4

STD70N2LH5 - STU70N2LH5 Electrical characteristics 3/12 2 Electrical characteristics (TCASE = 25°C unless otherwise specified) Table 4. Static Symbol Parameter Test conditions Min. Typ. Max. Unit V(BR)DSS Drain-source breakdown Voltage ID = 250 µA, VGS= 0 25 V IDSS Zero gate voltage drain current (VGS = 0) VDS = 25 V VDS = 25 V, TC = 125 °C 1 10 µA µA IGSS Gate body leakage current (VDS = 0) VGS = ± 22 V ±100 nA VGS(th) Gate threshold voltage VDS= VGS, ID = 250 µA 1 V RDS(on) Static drain-source on resistance VGS= 10 V, ID= 24 A SMD version 0.006 0.0071 Ω VGS= 10 V, ID= 24 A 0.0064 0.0075 Ω VGS= 5 V, ID= 24 A SMD version 0.008 0.01 Ω VGS= 5 V, ID= 24 A 0.0084 0.0104 Ω Table 5. Dynamic Symbol Parameter Test conditions Min Typ. Max. Unit Ciss Coss Crss Input capacitance Output capacitance Reverse transfer capacitance VDS =25 V, f=1 MHz, VGS=0 1300 300 50 pF pF pF Qg Qgs Qgd Total gate charge Gate-source charge Gate-drain charge VDD=15 V, ID = 48 A VGS =5 V (Figure 3) 8 TBD TBD nC nC nC Qgs1 Qgs2 Pre Vth gate-to-source charge Post Vth gate-to-source charge VDD=15 V, ID = 48 A VGS =5 V (Figure 8) TBD TBD nC nC RG Gate input resistance f=1 MHz gate bias Bias= 0 test signal level=20 mV open drain 1.1 Ω Ob so let e Pr od uc t(s ) - O bs let e Pr od uc t(s )

Page 5

Electrical characteristics STD70N2LH5 - STU70N2LH5 4/12 Table 6. Switching on/off (resistive load) Symbol Parameter Test conditions Min. Typ. Max. Unit td(on) tr Turn-on delay time Rise time VDD=10 V, ID= 24 A, RG=4.7 Ω, VGS= 10 V (Figure 2 and Figure 7) TBD TBD ns ns td(off) tf Turn-off delay time Fall time VDD=10 V, ID= 24 A, RG=4.7 Ω, VGS= 10 V (Figure 2 and Figure 7) TBD TBD ns ns Table 7. Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD ISDM Source-drain current Source-drain current (pulsed)(1) 1. Pulsed: pulse duration = 300µs, duty cycle 1.5% 48 192 A A VSD Forward on voltage ISD=24 A, VGS=0 1.1 V trr Qrr IRRM Reverse recovery time Reverse recovery charge Reverse recovery current ISD=48 A, di/dt =100 A/µs, VDD=20 V, Tj = 25 °C (Figure 4) TBD TBD TBD ns nC A Ob so let e Pr od uc t(s ) - O bs ole te P ro du ct( s)

Page 6

STD70N2LH5 - STU70N2LH5 Test circuit 5/12 3 Test circuit Figure 2. Switching times test circuit for resistive load Figure 3. Gate charge test circuit Figure 4. Test circuit for inductive load switching and diode recovery times Figure 5. Unclamped Inductive load test circuit Figure 6. Unclamped inductive waveform Figure 7. Switching time waveform Ob so let e Pr od uc t(s ) - O bs ole te P ro du ct( s)

Page 7

Test circuit STD70N2LH5 - STU70N2LH5 6/12 Figure 8. Gate charge waveform Ob so let e Pr od uc t(s ) - O bs ole te P ro du ct( s)

Page 8

STD70N2LH5 - STU70N2LH5 Package mechanical data 7/12 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com Ob so let e Pr od uc t(s ) - O bs ole te P ro du ct( s)

Page 9

Package mechanical data STD70N2LH5 - STU70N2LH5 8/12 DIM. mm. inch MIN. TYP MAX. MIN. TYP. MAX. A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A2 0.03 0.23 0.001 0.009 B 0.64 0.9 0.025 0.035 b4 5.2 5.4 0.204 0.212 C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 D1 5.1 0.200 E 6.4 6.6 0.252 0.260 E1 4.7 0.185 e 2.28 0.090 e1 4.4 4.6 0.173 0.181 H 9.35 10.1 0.368 0.397 L 1 0.039 (L1) 2.8 0.110 L2 0.8 0.031 L4 0.6 1 0.023 0.039 R 0.2 0.008 V2 0° 8° 0° 8° DPAK MECHANICAL DATA 0068772-F Ob so let e Pr od uc t(s ) - O bs ole te P ro du ct( s)

Page 10

STD70N2LH5 - STU70N2LH5 Package mechanical data 9/12 DIM. mm inch MIN. TYP. MAX. MIN. TYP. MAX. A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A3 0.7 1.3 0.027 0.051 B 0.64 0.9 0.025 0.031 B2 5.2 5.4 0.204 0.212 B3 0.85 0.033 B5 0.3 0.012 B6 0.95 0.037 C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 E 6.4 6.6 0.252 0.260 G 4.4 4.6 0.173 0.181 H 15.9 16.3 0.626 0.641 L 9 9.4 0.354 0.370 L1 0.8 1.2 0.031 0.047 L2 0.8 1 0.031 0.039 A C 2 C A 3 H A 1 D LL2 L1 1 3 = = B 3 B B 6 B 2 E G = = = = B 5 2 TO-251 (IPAK) MECHANICAL DATA 0068771-E Ob so let e Pr od uc t(s ) - O bs ole te P ro du ct( s)

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November 14, 2020

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November 13, 2020

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November 8, 2020

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STD70N2LH5 Guarantees

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